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Design of an 8 to 3 Encoder using 4 to 2 encoders as components

Problem 1: Design of a 4 to 2 Encoder (Behavioral)

We first design a 4 to 2 Encoder. Then using 4 to 2 Encoder we construct 8 to 3 Encoder.

 1 -- Encoder4To2.vhd
 2 -- O(1) is MSB
 3 -- O(0) is LSB
 4 library IEEE;
 5 use IEEE.std_logic_1164.all;
 6 
 7 entity Encoder4To2 is
 8     port( I:  in std_logic_vector(3 downto 0);
 9           O:   out std_logic_vector(1 downto 0)
10     );
11 end Encoder4To2;
12 
13 architecture EncIns of Encoder4To2 is
14 begin
15     O(1) <= I(1) OR I(0);
16     O(0) <= I(2) OR I(0);
17 end EncIns;

Problem: Design of an 8 to 3 Encoder (Structural)

Here's a diagram of 8 to 3 Encoder. In the image displayed below we see that input is a vector I which is a collection of 8 inputs (0 to 7). Output of 4 to 2 Encoder 1 are X0 and X1 and Output of 4 to 2 Encoder 2 are X2 and X3. Now a combinational logic which is implementation for several exressions calculates the output and store in vector O.

There's one special case to consider! There are 2 cases when output of X(0) = X(1) = X(2) = X(3) = 0. We have to give unique outputs for each case. To distinguish them we add I(4) in the expression of O(0).

Click the image to enlarge

 1 -- Encoder8To3.vhd
 2 library IEEE;
 3 use IEEE.std_logic_1164.all;
 4 
 5 entity Encoder8To3 is
 6     port( I:  in std_logic_vector(7 downto 0);
 7           O:   out std_logic_vector(2 downto 0)
 8     );
 9 end Encoder8To3;
10 
11 architecture EncIns of Encoder8To3 is
12 component Encoder4To2
13     port( CI:  in std_logic_vector(3 downto 0);
14           CO:   out std_logic_vector(1 downto 0)
15     );
16 end component;
17 
18 signal X: std_logic_vector(3 downto 0);
19 
20 begin
21     E1: Encoder4To2 port map(CI=>I(3 downto 0), CO => X(1 downto 0));
22     E2: Encoder4To2 port map(CI=>I(7 downto 4), CO => X(3 downto 2));
23 
24     O(0) <= X(0) or X(1) or I(4);
25     O(1) <= X(0) or X(2);
26     O(2) <= X(3) or X(3);
27 end EncIns;

Design of D Flip flop

Problem 1: Design a D Flip Flop Circuit (Behavioral)

 1 -- DFF.vhd
 2 entity DFF is
 3     port(CLK, Reset, DATA: in BIT;
 4                   Q: out BIT);
 5 end DFF;
 6 
 7 architecture DFFProc of DFF is
 8 begin
 9     p1: process (CLK, Reset)
10     begin
11         if (Reset = '1') then
12             Q <= '0';
13         elsif (CLK' event and CLK = '1') then
14             Q <= DATA;
15         end if;
16     end process p1;
17 end DFFProc;

Problem 2: Design a D Flip Flop Circuit (Structural)

 1 -- DFF_struct.vhd
 2 library IEEE;
 3 use IEEE.std_logic_1164.all;
 4 
 5 entity DFFStruct is
 6     port(CLK, Reset, DATA: in std_logic;
 7                   Q: out std_logic);
 8 end DFFStruct;
 9 
10 architecture DFFProc of DFFStruct is
11 component DFF
12     port(D, CLR, CLK:   in std_logic;
13               Output:   out std_logic);
14 end component;
15 
16 begin
17 DFFcomp1: DFF port map(D => DATA, CLR => Reset,
18                     CLK => CLK, Output => Q );
19 end DFFProc;