Designing Shifters and Rotators using VHDL

Problem 1: Design an 8 bit left rotator (Behavioral/Structural)

 1 -- LeftRotator.vhd
 2 -- 1 bit left rotator controlled by clock's rising edge
 3 -- to use rising_edge std_logic_1164 has to be imported
 4 -- the parameter of rising_edge() should be std_logic
 5 
 6 library IEEE;
 7 use IEEE.std_logic_1164.all;
 8 
 9 entity LR is
10     port(CLK:   in std_logic;
11     I:  in std_logic_vector(7 downto 0);
12     O:  out std_logic_vector(7 downto 0));
13 end LR;
14 
15 architecture LRins of LR is
16 begin
17     process
18     begin
19         wait until rising_edge(CLK);
20         O <= I (6 downto 0) & I(7);
21     end process;
22 end LRins;

Problem: Design a 8 bit device that can perform following operations on receiving according commands. (Behavioral/Structural)
when command input is
000 (reset) gives same ouput as input
001 left shift 1 bit
010 left shift 2 bit
011 right shift 1 bit
100 right shift 2 bit
101 left rotate 3 bit
110 right rotate 3 bit
111 swap left 4 bits with right

 1 -- shifterAndRotator.vhd
 2 -- 8 bit shifter and rotator with commands
 3 -- for operations for specific amount of bits to
 4 -- shift or rotate
 5 
 6 library IEEE;
 7 use IEEE.std_logic_1164.all;
 8 
 9 entity SR is
10     port(Input: in std_logic_vector(7 downto 0);
11            Cmd: in std_logic_vector(2 downto 0);
12         Output: out std_logic_vector(7 downto 0));
13 end SR;
14 
15 architecture SRIns of SR is
16 begin
17     with Cmd select
18     Output <= Input when "000",
19         Input(6 downto 0)&'0' when "001",
20         Input(5 downto 0)&"00" when "010",
21         Input(7 downto 1)&'0' when "011",
22         Input(7 downto 2)&"00" when "100",
23         Input(4 downto 0)&Input(7 downto 5) when "101",
24         Input(3 downto 0)&Input(7 downto 4) when "110",
25         Input(3 downto 0)&Input(7 downto 4) when "101";
26 end SRIns;