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Design of an 8 to 3 Encoder using 4 to 2 encoders as components

Problem 1: Design of a 4 to 2 Encoder (Behavioral)

We first design a 4 to 2 Encoder. Then using 4 to 2 Encoder we construct 8 to 3 Encoder.

 1 -- Encoder4To2.vhd
 2 -- O(1) is MSB
 3 -- O(0) is LSB
 4 library IEEE;
 5 use IEEE.std_logic_1164.all;
 6 
 7 entity Encoder4To2 is
 8     port( I:  in std_logic_vector(3 downto 0);
 9           O:   out std_logic_vector(1 downto 0)
10     );
11 end Encoder4To2;
12 
13 architecture EncIns of Encoder4To2 is
14 begin
15     O(1) <= I(1) OR I(0);
16     O(0) <= I(2) OR I(0);
17 end EncIns;

Problem: Design of an 8 to 3 Encoder (Structural)

Here's a diagram of 8 to 3 Encoder. In the image displayed below we see that input is a vector I which is a collection of 8 inputs (0 to 7). Output of 4 to 2 Encoder 1 are X0 and X1 and Output of 4 to 2 Encoder 2 are X2 and X3. Now a combinational logic which is implementation for several exressions calculates the output and store in vector O.

There's one special case to consider! There are 2 cases when output of X(0) = X(1) = X(2) = X(3) = 0. We have to give unique outputs for each case. To distinguish them we add I(4) in the expression of O(0).

Click the image to enlarge

 1 -- Encoder8To3.vhd
 2 library IEEE;
 3 use IEEE.std_logic_1164.all;
 4 
 5 entity Encoder8To3 is
 6     port( I:  in std_logic_vector(7 downto 0);
 7           O:   out std_logic_vector(2 downto 0)
 8     );
 9 end Encoder8To3;
10 
11 architecture EncIns of Encoder8To3 is
12 component Encoder4To2
13     port( CI:  in std_logic_vector(3 downto 0);
14           CO:   out std_logic_vector(1 downto 0)
15     );
16 end component;
17 
18 signal X: std_logic_vector(3 downto 0);
19 
20 begin
21     E1: Encoder4To2 port map(CI=>I(3 downto 0), CO => X(1 downto 0));
22     E2: Encoder4To2 port map(CI=>I(7 downto 4), CO => X(3 downto 2));
23 
24     O(0) <= X(0) or X(1) or I(4);
25     O(1) <= X(0) or X(2);
26     O(2) <= X(3) or X(3);
27 end EncIns;

Design of D Flip flop

Problem 1: Design a D Flip Flop Circuit (Behavioral)

 1 -- DFF.vhd
 2 entity DFF is
 3     port(CLK, Reset, DATA: in BIT;
 4                   Q: out BIT);
 5 end DFF;
 6 
 7 architecture DFFProc of DFF is
 8 begin
 9     p1: process (CLK, Reset)
10     begin
11         if (Reset = '1') then
12             Q <= '0';
13         elsif (CLK' event and CLK = '1') then
14             Q <= DATA;
15         end if;
16     end process p1;
17 end DFFProc;

Problem 2: Design a D Flip Flop Circuit (Structural)

 1 -- DFF_struct.vhd
 2 library IEEE;
 3 use IEEE.std_logic_1164.all;
 4 
 5 entity DFFStruct is
 6     port(CLK, Reset, DATA: in std_logic;
 7                   Q: out std_logic);
 8 end DFFStruct;
 9 
10 architecture DFFProc of DFFStruct is
11 component DFF
12     port(D, CLR, CLK:   in std_logic;
13               Output:   out std_logic);
14 end component;
15 
16 begin
17 DFFcomp1: DFF port map(D => DATA, CLR => Reset,
18                     CLK => CLK, Output => Q );
19 end DFFProc;

Designing Shifters and Rotators using VHDL

Problem 1: Design an 8 bit left rotator (Behavioral/Structural)

 1 -- LeftRotator.vhd
 2 -- 1 bit left rotator controlled by clock's rising edge
 3 -- to use rising_edge std_logic_1164 has to be imported
 4 -- the parameter of rising_edge() should be std_logic
 5 
 6 library IEEE;
 7 use IEEE.std_logic_1164.all;
 8 
 9 entity LR is
10     port(CLK:   in std_logic;
11     I:  in std_logic_vector(7 downto 0);
12     O:  out std_logic_vector(7 downto 0));
13 end LR;
14 
15 architecture LRins of LR is
16 begin
17     process
18     begin
19         wait until rising_edge(CLK);
20         O <= I (6 downto 0) & I(7);
21     end process;
22 end LRins;

Problem: Design a 8 bit device that can perform following operations on receiving according commands. (Behavioral/Structural)
when command input is
000 (reset) gives same ouput as input
001 left shift 1 bit
010 left shift 2 bit
011 right shift 1 bit
100 right shift 2 bit
101 left rotate 3 bit
110 right rotate 3 bit
111 swap left 4 bits with right

 1 -- shifterAndRotator.vhd
 2 -- 8 bit shifter and rotator with commands
 3 -- for operations for specific amount of bits to
 4 -- shift or rotate
 5 
 6 library IEEE;
 7 use IEEE.std_logic_1164.all;
 8 
 9 entity SR is
10     port(Input: in std_logic_vector(7 downto 0);
11            Cmd: in std_logic_vector(2 downto 0);
12         Output: out std_logic_vector(7 downto 0));
13 end SR;
14 
15 architecture SRIns of SR is
16 begin
17     with Cmd select
18     Output <= Input when "000",
19         Input(6 downto 0)&'0' when "001",
20         Input(5 downto 0)&"00" when "010",
21         Input(7 downto 1)&'0' when "011",
22         Input(7 downto 2)&"00" when "100",
23         Input(4 downto 0)&Input(7 downto 5) when "101",
24         Input(3 downto 0)&Input(7 downto 4) when "110",
25         Input(3 downto 0)&Input(7 downto 4) when "101";
26 end SRIns;

Adder Design using VHDL

Problem 1: Design a Half Adder (Behavioral)

 1 -- HALF_Adder_behavioral.vhd
 2 entity Half_Adder is
 3     port(
 4         A,B: in BIT;
 5         S, C: out BIT
 6     );
 7 end Half_Adder;
 8 
 9 architecture struct of Half_Adder is
10 begin
11     S <= A xor B;
12     C <= A and B;
13 end struct;

Problem 2: Design a Full Adder using Half Adders as components (Behavioral/Structural)

 1 -- FullAdder_Structural.vhd
 2 entity FULL_ADDER is
 3     port(A,B,C: in BIT;
 4         S, Cout:    out BIT);
 5 end FULL_ADDER;
 6 
 7 architecture FAIns of FULL_ADDER is
 8     component HALF_ADDER
 9     port(I1, I2: in BIT;
10         Carry, Sum:    out BIT);
11     end component;
12 
13     component OR_GATE
14         port(I1,I2: in BIT;
15                 O:  out BIT);
16     end component;
17     signal X1, X2, X3:  BIT;
18 
19 begin
20     HA1: HALF_ADDER port map (
21         I1 => A, I2 => B, Carry => X1, Sum => X2);
22     HA2: HALF_ADDER port map (
23         I1 => X2, I2 => C, Carry => X3, Sum => S);
24     OR1: OR_GATE    port map(
25         I1 => X1, I2 => X3, O => Cout);
26 end FAIns;

Multiplexors Design in VHDL

Problem 1: Design a 2 to 1 Multiplexor (Behavioral/Structural)

 1 -- Mux2To1.vhd
 2 entity Mux2To1 is
 3     port ( Ain, Bin, Sin:   in BIT;
 4                     Yout:    out BIT
 5     );
 6 end Mux2to1;
 7 
 8 architecture MuxIns of Mux2To1 is
 9 begin
10     Yout <= (Ain and (not Sin)) or (Bin and Sin);
11 end MuxIns;

Problem: Design a 4 to 1 Multiplexor (Behavioral/Structural)

 1 -- Mux4To1.vhd
 2 -- case must be inside a process
 3 entity Mux4To1 is
 4     port ( I:   in BIT_VECTOR(3 downto 0);
 5          Sin:   in BIT_VECTOR(1 downto 0);
 6      Mux_out:   out BIT
 7     );
 8 end Mux4to1;
 9 
10 architecture MuxIns of Mux4To1 is
11 begin
12     p1: process (I, Sin)
13     begin
14         case Sin is
15             when "00" =>
16                 Mux_out <= I (3);
17             when "01" =>
18                 Mux_out <= I (2);
19             when "10" =>
20                 Mux_out <= I (1);
21             when "11" =>
22                 Mux_out <= I (0);
23         end case;
24     end process p1;
25 end MuxIns;

VHDL Half Adder and Full Adder Design

Problem: Design a Half Adder (Behavioral)

 1 -- HALF_Adder_behavioral.vhd
 2 entity Half_Adder is
 3     port(
 4         A,B: in BIT;
 5         S, C: out BIT
 6     );
 7 end Half_Adder;
 8 
 9 architecture struct of Half_Adder is
10 begin
11     S <= A xor B;
12     C <= A and B;
13 end struct;

Problem: Design a Full Adder using Half Adders components (Structural)

 1 -- FullAdder_Structural.vhd
 2 entity FULL_ADDER is
 3     port(A,B,C: in BIT;
 4         S, Cout:    out BIT);
 5 end FULL_ADDER;
 6 
 7 architecture FAIns of FULL_ADDER is
 8     component HALF_ADDER
 9     port(I1, I2: in BIT;
10         Carry, Sum:    out BIT);
11     end component;
12 
13     component OR_GATE
14         port(I1,I2: in BIT;
15                 O:  out BIT);
16     end component;
17     signal X1, X2, X3:  BIT;
18 
19 begin
20     HA1: HALF_ADDER port map (
21         I1 => A, I2 => B, Carry => X1, Sum => X2);
22     HA2: HALF_ADDER port map (
23         I1 => X2, I2 => C, Carry => X3, Sum => S);
24     OR1: OR_GATE    port map(
25         I1 => X1, I2 => X3, O => Cout);
26 end FAIns;

VHDL: 2 To 4 Decoder(Behavioral), 3 To 8 Decoder (Structural) - redirect

The post has moved here:
https://sa-blog.azurewebsites.net/post/2010/05/06/vhdl-2-to-4-decoder-behavioral-3-to-8-decoder-structural

Windows Seven: "Windows could not start the Windows Event Log Service on Local Computer" and winsock

Today I sat on my PC like other days. It took long time to boot into The Windows Seven Desktop. When it booted it showed an error notification.

"Failed to connect to a windows service - Windows could not connect to the System Event Notification service. This problem prevents limited users from logging on to the system. As an administrator user, you can review the System Event Log for details about why the service didn't respond."

So I tried to enable system event log service myself from services.msc. It reported another error!

Windows could not start the Windows Event Log Service on Local Computer

Error 1747: the authentication service is unknown.

Also I got an error when trying to activate network interface.
Unable to Initialize Windows Sockets Interface


I tried manythings. Like I was thinking if Kaspersky Internet Security has got the control. So uninstall it. Tried to enable, disable couple of services. Nothing solved it.

Finally the trick of resetting socket interface really worked. To reset the socket interface I opened a command prompt by clicking run as administrator. Then applied the following command.

C:> netsh winsock reset

Then I restarted the PC. Everything got fixed. It saved the day.