Design of D Flip flop

Problem 1: Design a D Flip Flop Circuit (Behavioral)

 1 -- DFF.vhd
 2 entity DFF is
 3     port(CLK, Reset, DATA: in BIT;
 4                   Q: out BIT);
 5 end DFF;
 6 
 7 architecture DFFProc of DFF is
 8 begin
 9     p1: process (CLK, Reset)
10     begin
11         if (Reset = '1') then
12             Q <= '0';
13         elsif (CLK' event and CLK = '1') then
14             Q <= DATA;
15         end if;
16     end process p1;
17 end DFFProc;

Problem 2: Design a D Flip Flop Circuit (Structural)

 1 -- DFF_struct.vhd
 2 library IEEE;
 3 use IEEE.std_logic_1164.all;
 4 
 5 entity DFFStruct is
 6     port(CLK, Reset, DATA: in std_logic;
 7                   Q: out std_logic);
 8 end DFFStruct;
 9 
10 architecture DFFProc of DFFStruct is
11 component DFF
12     port(D, CLR, CLK:   in std_logic;
13               Output:   out std_logic);
14 end component;
15 
16 begin
17 DFFcomp1: DFF port map(D => DATA, CLR => Reset,
18                     CLK => CLK, Output => Q );
19 end DFFProc;