Problem 1: Design a Half Adder (Behavioral)

Problem 2: Design a Full Adder using Half Adders as components (Behavioral/Structural)

1 -- HALF_Adder_behavioral.vhd 2 entity Half_Adder is 3 port( 4 A,B: in BIT; 5 S, C: out BIT 6 ); 7 end Half_Adder; 8 9 architecture struct of Half_Adder is 10 begin 11 S <= A xor B; 12 C <= A and B; 13 end struct;

Problem 2: Design a Full Adder using Half Adders as components (Behavioral/Structural)

1 -- FullAdder_Structural.vhd 2 entity FULL_ADDER is 3 port(A,B,C: in BIT; 4 S, Cout: out BIT); 5 end FULL_ADDER; 6 7 architecture FAIns of FULL_ADDER is 8 component HALF_ADDER 9 port(I1, I2: in BIT; 10 Carry, Sum: out BIT); 11 end component; 12 13 component OR_GATE 14 port(I1,I2: in BIT; 15 O: out BIT); 16 end component; 17 signal X1, X2, X3: BIT; 18 19 begin 20 HA1: HALF_ADDER port map ( 21 I1 => A, I2 => B, Carry => X1, Sum => X2); 22 HA2: HALF_ADDER port map ( 23 I1 => X2, I2 => C, Carry => X3, Sum => S); 24 OR1: OR_GATE port map( 25 I1 => X1, I2 => X3, O => Cout); 26 end FAIns;

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