Multiplexors Design in VHDL

Problem 1: Design a 2 to 1 Multiplexor (Behavioral/Structural)

 1 -- Mux2To1.vhd
 2 entity Mux2To1 is
 3     port ( Ain, Bin, Sin:   in BIT;
 4                     Yout:    out BIT
 5     );
 6 end Mux2to1;
 7 
 8 architecture MuxIns of Mux2To1 is
 9 begin
10     Yout <= (Ain and (not Sin)) or (Bin and Sin);
11 end MuxIns;

Problem: Design a 4 to 1 Multiplexor (Behavioral/Structural)

 1 -- Mux4To1.vhd
 2 -- case must be inside a process
 3 entity Mux4To1 is
 4     port ( I:   in BIT_VECTOR(3 downto 0);
 5          Sin:   in BIT_VECTOR(1 downto 0);
 6      Mux_out:   out BIT
 7     );
 8 end Mux4to1;
 9 
10 architecture MuxIns of Mux4To1 is
11 begin
12     p1: process (I, Sin)
13     begin
14         case Sin is
15             when "00" =>
16                 Mux_out <= I (3);
17             when "01" =>
18                 Mux_out <= I (2);
19             when "10" =>
20                 Mux_out <= I (1);
21             when "11" =>
22                 Mux_out <= I (0);
23         end case;
24     end process p1;
25 end MuxIns;