VHDL: 2 To 4 Decoder(Behavioral), 3 To 8 Decoder (Structural)

VHDL Code 2 to 4 Decoder Behavioral

 1 -- Decoder2To4_Behavioral.vhd
 2 entity Decoder2to4 is
 3     port (A,B:  in BIT;
 4             O:  out BIT_VECTOR(3 downto 0));
 5 end Decoder2To4;
 6 
 7 architecture DecIns of Decoder2To4 is
 8 begin
 9     O(3) <= (not A) and (not B);
10     O(2) <= (not A) and B;
11     O(1) <= A and (not B);
12     O(0) <= A and B;
13 end DecIns;

VHDL Code 3 to 8 Decoder (Structural) using 2 To 4 as component

 1 -- Decoder3To8.vhd
 2 -- Using Decoder 2 To 4 as component
 3 
 4 entity Decoder3To8 is
 5     port( A,B,C:    in BIT;
 6             O:      out BIT_VECTOR(7 downto 0));
 7 end Decoder3To8;
 8 
 9 architecture DecIns of Decoder3To8 is
10 component Decoder2to4
11     port (I1, I2:   in BIT;
12             Odec:   out BIT_VECTOR(3 downto 0));
13 end component;
14 signal X1: BIT_VECTOR(3 downto 0);
15 
16 
17 begin
18 Dec2To4_1:
19     Decoder2To4 port map(I1 => A, I2 => B, Odec(3 downto 0) => X1 (3 downto 0));
20 
21     O(0) <= X1(0) and C;
22     O(1) <= X1(1) and C;
23     O(2) <= X1(2) and C;
24     O(3) <= X1(3) and C;
25 
26     O(4) <= X1(0) and (not C);
27     O(5) <= X1(1) and (not C);
28     O(6) <= X1(2) and (not C);
29     O(7) <= X1(3) and (not C);
30 end DecIns;